Notes from Work:
Today my team manager, Balan Shreeharsha, shared an interesting article. It has something to do with Chip testing for checking ESD (Electro Static Discharge) effects. Normally, when a silicon is back, silicon validation and other tests on the first lot happen in parallel. Several tests are conducted for validating silicon starting from identifying manufacturing defects to checking each device for ESD effects. The article talks about ESD Sensitivity test.
Any reasonable study on industry practices reveals how important ESD test is. Just due to ESD failures, many chips dont even make it to market. The best example of electro static discharge is lightning. If you are interested to know more, read about Tesla coil. Here it is mandatory to mention that without Tesla, we would have never understood Electro Static Charge with so much clarity.
Anyway, we digress! Coming back to the point, every chip is tested for how well it can discharge electro static charge that it accumulates naturally without affecting the circuit inside the package. A lot of research went into this field. ESD is generally taken very seriously by electronic industry especially due to the damage it can cause to the circuit and possible malfunctions involved. So, to test devices for ESD, specific simulation models are used. These simulation models, which are actually circuits, create the situations similar to the real world. Two of the most used models are Human Body Model and Machine Model. These simulation models help in determining whether the device can handle ESD into the device. However, ESD can happen from the device, especially when the device accumulates the charge and discharges it instantaneously when it comes in contact with another conducting body.
I actually didnt know much about the second case. The article that my manager shared described this case. It is called “Charged Device Model”. The article describes Charged Device Model patently and gives two widely used simulation models as examples – Socketted Device Model and Real-world Charged Device Model.The article explains them as
There are currently two widely-used models for CDM testing: 1) the Socketted Discharge Model (SDM); and 2) the Real-world Charged Device Model (RCDM).
In SDM, the device is placed in a power socket and charged from a high voltage source.Then it is discharged through a 1 ohm resistor. In RCDM, the device is placed in “deadbug position” on a thin di-electric, which is then placed over a ground plate. The device is then charged using a induction field or by a charging probe.Then each pin of the device is discharged through a 1 ohm resistor. If the device survives without damaging the circuit, it is accepted as a good device.
An interesting point to understand will be “how and why is RCDM a better simulation model compared to SDM”. First thing that comes to my mind is in SDM, the device is inside a socket and there is no way to ensure that the device is getting charged to the fullest. In RCDM, due to the use of di-electric and placement of the device in deadbug position, it is ensured that device charges to the fullest, there by checking for the worst case scenario. This is an area where I think there is more to learn.
More than the details of SDM and RCDM what tickled most of my colleagues who are unaware of RCDM ESD testing, like me, is the term “deadbug position”. Just what is deadbug position!? Further digging (thanks to Google) reveals this
Placing the DUT with the pin side up (dead bug position) produces a capacitance between the DUT and the field plate that scales with the size of the DUT. A low inductance discharge path to ground is formed by moving the ground plane relative to the field plate such that the pogo pin can touch any pin on the DUT. The 1Ω resistor and coaxial cable provide a low inductance current sensor so that discharge waveforms can be conveniently measured.
So “deadbug position” is that position where device lies on its back and pins are in upward direction. Due to the use of Pogo pin, it is taken care that discharge through each pin is checked. Another aspect which can be observed here is how one can use induction field to charge the device. This primarily made possible by the capacitance created between the device and field plate. The pogo pin finally allows for probing the pins and thus one can see waveform of discharge on an oscilloscope. I must say “deadbug position” is cool.
What is even more interesting is “deadbug position is also a term used in gymnasiums“.
Another interesting aspect of VLSI and electronics, duly noted.
Image Courtesy: www.conformity.com